This invention is directed to a system for correcting induced wafer magnification errors which could cause potential mis-registration between lithographic levels in the fabrication of a semiconductor device. In particular, this invention employs the application of transverse electric fields to control the dimensions of a piezoelectric film which is deposited on a conductive X-ray lithography mask substrate.
In the manufacture of semiconductor devices, X-ray lithography has been pursued as a technique of choice for devices having submicron line widths. The lithography technique replicates a desired pattern from masks to various layers deposited on a semiconductor wafer. Different masks are used in different processing steps of the wafer. Given the extreme dimensional requirements (submicron) it is therefore of critical importance that the alignment of each mask relative to the wafer be held within very tightly controlled tolerances.
As an example of the type of errors which occur, are process induced wafer magnification errors. These errors can cause a mis-registration between various lithographic levels, that is between the wafer and various masks. The control of mask alignment is an important parameter in reducing such errors. It has been proposed to use piezoelectric thin films deposited on the X-ray substrate to achieve mask to registration registration by the use of applied electric fields. To achieve directional control of the dimensions of a piezoelectric thin film, fields which are applied along the plane of substrate (transverse) are considered advantageous. This is because when the fields are applied longitudinally (i.e., through the thickness of the film). the transverse dimensional change in the plane is a function of the film's crystalline structure. That is, the change may in some cases be isotropic for amorphous or a polycrystalline materials. Additionally, the transverse dimensional change is reduced in magnitude as a function of the materials Poisson's ratio.
Thus, the use of transverse electric fields is preferable for piezoelectric films deposited on a dielectric mask substrate. In the case of piezoelectric films deposited on conductive substrates, the transverse fields are non-uniform. This is because of the large voltage drop between the top and bottom of the film when combined with the presence of an equipotential bottom surface. To minimize the radiation damage effects, electrically conductive mask substrates may be required. Within existing technology there is no acceptable technique which uses a transverse electric field to control piezoelectric films to correct for magnification errors in the case of electrically conductive substrates.
Within the art a variety of other techniques have been proposed to achieve alignment of lithography masks. However, none deals specifically with the use of piezoelectric thin films as a technique of correcting for magnification errors. For example. U.S. Pat. No. 4,694,477 employs X-ray lithography masks. Positioning is by piezoelectric transducers which are positioned external to the masks. Thus in accordance with this proposal the masks and frame are attached to a stage plate which has six degrees of freedom. Positioning of the plate is by use of piezoelectric transducers. While the mask is aligned there is no dimensional control of the mask itself.
Other techniques to align a photocathode mask by the use of piezoelectric techniques are disclosed in U.S. Pat. No. 3,887,811. In contrast to the technique employed in the '477 patent, U.S. Pat. No. 3,887,881 provides angular alignment by the use of piezoelectric elements that cause relative rotation between the photocathode mask and the wafer. Thus, mask rotation occurs by the use of an externally generated force such that physical movement occurs.
Dimensional control by use of temperature change is disclosed in U.S. Pat. No. 4,256,829 and EPO No. 054 641. In the '829 patent the substrate and masks errors are adjusted by local temperature change to account for any planar dimensional distortion which will exist between various processing steps. In the EP-641 disclosure a shadow mask is constructed having a series of through-holes or vias. The mask and wafer are thus deliberately constructed in mis-registration at room temperature but the vias will be aligned when the mask reaches its working temperature. Misalignment is compensated by anticipating the difference in thermal expansion between the mask and wafer. Should there be a variation in pre-calculation temperatures then, registration will not be achieved.